Our link adaptation IP improves the spectrum efficiency in the carrier aggregation system of 5G networks by improving aggregate cell throughput in scenarios of underground traffic tunnels, large indoor space, urban outdoor and suburban remote areas, for elevated service quality by wireless network operators. The spectrum management in multi-radio multi-band system is challenging for network equipment design and our link adaptation IP addresses this technical challenge. 

Our link adaptation IP features an enhanced computation engine to compute the modulation and coding schemes in a more accurate way compared to conventional link adaptation in low SNR conditions. The conventional SNR-threshold based link adaptation applies a SNR shift value to offset the noise effect, however, this offsets can be inaccurate in predicting optimal modulation and coding schemes in link adaptation. Our IP has enhanced design thus improving the physical layer throughput performance under low SNR conditions.

The link adaptation software IP adapts the transmitter configurations at 5G basestation, according to the channel conditions. The channel state information estimates and the channel parameter estimates based on channel feedback from the UE and the uplink channel estimates, are processed by the link adaptation algorithm. This software IP is part of L2 software to improve the L1 physical layer throughput performance under time-varying wireless channel conditions.

The IP core supports the 5G NR LDPC encoding and decoding architecture specified in 3GPP TS 38.212, including Base Graph 1 and Base Graph 2 with lifting sizes ranging from 2 to 384. Built on a highly configurable LDPC framework, the architecture provides a scalable RTL IP for future expansion to 6G LDPC coding schemes and additional base graph configurations. The RTL cores are verified by UVM-based verification setups based on AWGN channel to ensure robustness and production-quality reliability. 

The RTL development follows industry-standard verification methodologies based on UVM testbench evaluation. The LDPC hardware accelerator RTL modules are validated through AWGN channel performance testing, with their error-correction performance compared against an independent LDPC software simulation reference model. This verification approach ensures that the RTL implementation achieves performance matching with the software simulation results.

The LDPC decoder adopts optimized algorithms and architectures to address latency and throughput performance requirements of 5G basestation. The LDPC decoder accelerator is designed to achieve ultra-high throughput and low-latency decoding performance, enabling the real-time processing requirements of 5G infrastructure. The decoder architecture is optimized through efficient pipelining and parallel processing to ensure the IP core is well suited for FPGA and ASIC implementations in 5G advanced and 6G systems.

Our hybrid beamforming IP supports high-throughput and low-latency 5G applications by operating in both digital and analog domains. The system features beamforming weighting computation for both transmitter beamforming and receiver beamforming on the same equipment, and has a flexible design that can be scaled up to support 6G hybrid beamforming with massive analog antenna arrays according to latest discussions from 3GPP standardization meetings. 

The system evaluation is done across representative wireless system bands. Testing scenarios include a 5G frequency range 1 configuration of 64 transmit antennas at 3.5 GHz, and a 5G millimeter-wave setup with 256 transmit antennas at 28 GHz. The evaluation framework extends to 6G millimeter-wave system at 28 GHz with an antenna array of 1024 transmit antennas. The hybrid beamforming architecture is designed to support multi-radio and multi-band operations in 5G and 6G networks.